Low Power Area-Efficient Adiabatic Vedic Multiplier
نویسندگان
چکیده
منابع مشابه
Area Efficient Low Power Vedic Multiplier Design Using GDI Technique
Multipliers consume maximum amount of power during the partial product addition. For higher order multiplication, a huge number of adders are used to perform the partial product addition. Using compressor adders, that can add four, five , six or seven bits at a time, the number of full adders and half adders can be reduced and thus area and power consumed also gets reduced. These compressor add...
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ژورنال
عنوان ژورنال: International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
سال: 2014
ISSN: 2320-3765,2278-8875
DOI: 10.15662/ijareeie.2014.0308018